1. Field of the Invention
The present invention generally relates to a successive comparison analog-to-digital (A-D) converter. More particularly, the present invention relates to a charge-redistributing type successive comparison A-D converter.
2. Description of Related Art
With recent improvement in digital processing speed, high speed operation is required for an A-D converter serving as an interface between analog and digital signals. FIG. 4 is a block diagram of the structure of a common successive comparison A-D converter. In the successive comparison A-D converter of FIG. 4, a sample-and-hold section 1 samples and holds an analog input, and a voltage comparator 2 compares the analog input with a voltage from a local digital-to-analog (D-A) converter 3. A latch circuit 4 latches the output of the voltage comparator 2. A state control circuit 5 controls the output of the local D-A converter 3 based on the output of the voltage comparator 2. The voltage comparator 2 successively compares the voltages from the MSB (most significant bit). When the voltage comparator 2 completes the voltage comparison to the LSB (least significant bit), the latch circuit 4 outputs a latched digital value.
A charge-redistributing type successive comparison A-D converter is known as an A-D converter capable of obtaining a large number of converted bits with a small size. FIG. 5 shows the structure of a conventional charge-redistributing type successive comparison A-D converter. The successive comparison A-D converter of FIG. 5 is a 3-bit A-D converter, and includes a capacitor array 29, analog switch groups 30 to 32, a voltage comparator 27, and a state control circuit 28. Note that the latch circuit 4 in FIG. 4 is not shown in FIG. 5. The capacitor array 29 includes capacitors 11 to 14. The capacitors 11 to 14 have a capacitance 4C, 2C, C, C, respectively, where C is a unit capacitance. The analog switch group 30 connects the capacitor array 29 to an analog input Vin. The analog switch group 30 includes analog switches 15 to 18. The analog switches 15 to 18 have an on-state resistance R. The analog switch group 31 connects the capacitor array 29 to a higher reference voltage Vrh (in the illustrated example, power supply voltage Vdd). The analog switch group 31 includes analog switches 19 to 22. The analog switches 19 to 22 have an on-state resistance R. The analog switch group 32 connects the capacitor array 29 to a lower reference voltage Vrl (in the illustrated example, ground voltage GND). The analog switch group 32 includes analog switches 23 to 26. The analog switches 23 to 26 have an on-state resistance R. The voltage comparator 27 includes an analog switch 33 and an inverter 34. The state control circuit 28 controls ON/OFF of the analog switches 15 to 26, 33.
Hereinafter, operation of the successive comparison A-D converter in FIG. 5 will be described.
First, the analog switch group 30 and the analog switch 33 are turned ON, and the analog input Vin is sampled and held in the capacitor array 29. Provided that the inverter 34 has a threshold voltage Vth, charges Q0 accumulated in the capacitor array 29 are defined by the following equation:
Q0=8C(Vthxe2x88x92Vin)xe2x80x83xe2x80x83(1).
The time required for the sample-and-hold operation is determined by a time constant 4CR of the capacitor 11 and the analog switch 15.
When the sample-and-hold operation is completed, the analog switches 15 to 18, 33 are turned OFF, and the accumulated charges Q0 are stored on the side of the voltage comparator 27 in the capacitor array 29.
The successive comparison A-D converter then proceeds to operation of comparing the MSB (bit 2). In this operation, the analog switches 19, 24 to 26 are turned ON and the charges Q0 are redistributed to the capacitor array 29. An input voltage Vx to the inverter 34 is defined by the following equation according to the principle of conservation of charge:
Vx=Vthxe2x88x92(Vinxe2x88x92(xc2xd)Vdd)xe2x80x83xe2x80x83(2).
For Vin greater than (xc2xd)Vdd, the voltage comparator 27 outputs xe2x80x9cHixe2x80x9d, and the MSB is determined as xe2x80x9c1xe2x80x9d. For Vin less than (xc2xd)Vdd, the voltage comparator 27 outputs xe2x80x9cLowxe2x80x9d, and the MSB is determined as xe2x80x9c0xe2x80x9d.
After the MSB is determined, the successive comparison A-D converter proceeds to operation of comparing the following bit (bit 1). When the voltage comparison output of the MSB is xe2x80x9cHixe2x80x9d, the analog switches 19, 20, 25, 26 are turned ON. On the other hand, when the voltage comparison output of the MSB is xe2x80x9cLowxe2x80x9d, the analog switches 23, 20, 25, 26 are turned ON. It is herein assumed that the voltage comparison output of the MSB is xe2x80x9cHixe2x80x9d. In this case, the analog switches 19, 20, 25, 26 are turned ON and the charges Q0 are redistributed to the capacitor array 29. An input voltage Vx to the inverter 34 is defined by the following equation according to the principle of conservation of charge:
Vx=Vthxe2x88x92(Vinxe2x88x92(xc2xe)Vdd)xe2x80x83xe2x80x83(3).
For Vin greater than (xc2xe)Vdd, the voltage comparator 27 outputs xe2x80x9cHixe2x80x9d, and bit 1 is determined as xe2x80x9c1xe2x80x9d. For Vin less than (xc2xe)Vdd, the voltage comparator 27 outputs xe2x80x9cLowxe2x80x9d, and bit 1 is determined as xe2x80x9c0xe2x80x9d.
After bit 1 is determined, the successive comparison A-D converter proceeds to operation of comparing the following bit, LSB (bit 0). When the voltage comparison output of bit 1 is xe2x80x9cHixe2x80x9d, the analog switches 19, 20, 21, 26 are turned ON. On the other hand, when the voltage comparison output of bit 1 is xe2x80x9cLowxe2x80x9d, the analog switches 19, 24, 21, 26 are turned ON. It is herein assumed that the voltage comparison output of bit 1 is xe2x80x9cLowxe2x80x9d. In this case, the analog switches 19, 24, 21, 26 are turned ON and the charges Q0 are redistributed to the capacitor array 29. An input voltage Vx to the inverter 34 is defined by the following equation according to the principle of conservation of charge:
Vx=Vthxe2x88x92(Vinxe2x88x92(⅝)Vdd)xe2x80x83xe2x80x83(4).
For Vin greater than (⅝)Vdd, the voltage comparator 27 outputs xe2x80x9cHixe2x80x9d, and the LSB is determined as xe2x80x9c1xe2x80x9d. For Vin less than (⅝)Vdd, the voltage comparator 27 outputs xe2x80x9cLowxe2x80x9d, and bit 1 is determined as xe2x80x9c0xe2x80x9d.
Charges are redistributed when every bit is determined. The time required for such charge redistribution is equal to that required for the sample-and-hold operation, and determined by a time constant 4CR of the capacitor 11 and the on-state resistance of the analog switch 19 or 23.
The successive comparison A-D converter in FIG. 5 has different time constants 4CR, 2CR, CR, CR for the capacitors 11 to 14 of the capacitor array 29, respectively. For the capacitor 11, each of the time required to sample and hold the analog input Vin and the time required for charge redistribution is therefore four times that for the capacitor 14. Accordingly, the A-D converter can operate only at about a quarter of the maximum possible speed. In other words, in the case of an N-bit A-D converter, the operation speed is reduced to at most xc2xd(Nxe2x88x921).
It is an object of the present invention to provide a successive comparison A-D converter capable of improving the operation speed.
According to one aspect of the present invention, a successive comparison A-D converter includes a plurality of capacitors, a plurality of first analog switches, a plurality of second analog switches, a plurality of third analog switches, a voltage comparator, and a state controller. The plurality of capacitors have their respective one electrodes connected to each other. Each of the plurality of capacitors has a capacitance weighted with a prescribed weighting factor. The plurality of first analog switches are provided corresponding to the plurality of capacitors. Each of the plurality of first analog switches is connected between the other electrode of a corresponding capacitor and a first node. The first node receives an analog input. The plurality of second analog switches are provided corresponding to the plurality of capacitors. Each of the plurality of second analog switches is connected between the other electrode of a corresponding capacitor and a second node. The second node receives a first reference voltage. The plurality of third analog switches are provided corresponding to the plurality of capacitors. Each of the plurality of third analog switches is connected between the other electrode of a corresponding capacitor and a third node. The third node receives a second reference voltage that is lower than the first reference voltage. The voltage comparator compares a voltage at the respective one electrodes of the plurality of capacitors with a third reference voltage. The state controller controls ON/OFF of the plurality of first analog switches, the plurality of second analog switches and the plurality of third analog switches based on the comparison result of the voltage comparator. Each of the plurality of first analog switches has an on-state resistance weighted with a prescribed weighting factor.
In the above successive comparison A-D converter, a first analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor, whereby a time constant of this capacitor can be reduced. As a result, the difference in time constant between the capacitors is reduced. This enables reduction in time required to precharge (sample and hold) the analog input, improving the A-D conversion speed.
Preferably, each of the plurality of first analog switches has an on-state resistance weighted with an inverse number of the weighting factor for the capacitance of a corresponding capacitor.
In the above successive comparison A-D converter, the respective time constants of the capacitors are equal to each other. Accordingly, the time required to charge/discharge each capacitor is the same. This prevents reduction in operation speed caused by the difference in time constant between the capacitors. Moreover, the A-D conversion can be improved while suppressing increase in circuit area.
Preferably, each of the plurality of first analog switches includes a MOS (metal oxide semiconductor) transistor. Each MOS transistor is connected between the other electrode of a corresponding capacitor and the first node. The MOS transistor included in one of the plurality of first analog switches and the MOS transistor included in another first analog switch have different channel widths and/or different channel lengths.
When the MOS transistor is operating in a linear region, the on-state resistance is inversely proportional to the channel width and is proportional to the channel length. In the above successive comparison A-D converter, the MOS transistor included in one first analog switch and the MOS transistor included in another first analog switch have different channel widths and/or different channel lengths. This enables the on-state resistance of these first analog switches to be weighted with different weighting factors. Accordingly, a first analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor. Moreover, the respective time constants of the capacitors can be made equal to each other.
Preferably, each of the plurality of first analog switches includes one or a plurality of fourth analog switches. One or the plurality of fourth analog switches are connected in parallel between the other electrode of a corresponding capacitor and the first node. The number of fourth analog switches included in one of the plurality of first analog switches is different from that included in another first analog switch.
The above successive comparison A-D converter enables the on-state resistance of one first analog switch and another first analog switch to be weighted with different weighting factors. Accordingly, a first analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor. Moreover, the respective time constants of the capacitors can be made equal to each other.
Preferably, each of the plurality of first analog switches includes a MOS transistor. Each MOS transistor is connected between the other electrode of a corresponding capacitor and the first node. A gate voltage to be applied to the MOS transistor included in one of the plurality of first analog switches when the MOS transistor is in an ON state is different from that to be applied to the MOS transistor included in another first analog switch when the MOS transistor is in an ON state.
When the MOS transistor is operating in a linear region, the on-state resistance is inversely proportional to the gate voltage. In the above successive comparison A-D converter, a gate voltage to be applied to the MOS transistor included in one first analog switch when the MOS transistor is in an ON state is different from that to be applied to the MOS transistor included in another first analog switch when the MOS transistor is in an ON state. This enables the on-state resistance of the first analog switches to be weighted with different weighting factors. Accordingly, a first analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor. Moreover, the respective time constants of the capacitors can be made equal to each other.
According to another aspect of the present invention, a successive comparison A-D converter includes a plurality of capacitors, a plurality of first analog switches, a plurality of second analog switches, a plurality of third analog switches, a voltage comparator, and a state controller. The plurality of capacitors have their respective one electrodes connected to each other. Each of the plurality of capacitors has a capacitance weighted with a prescribed weighting factor. The plurality of first analog switches are provided corresponding to the plurality of capacitors. Each of the plurality of first analog switches is connected between the other electrode of a corresponding capacitor and a first node. The first node receives an analog input. The plurality of second analog switches are provided corresponding to the plurality of capacitors. Each of the plurality of second analog switches is connected between the other electrode of a corresponding capacitor and a second node. The second node receives a first reference voltage. The plurality of third analog switches are provided corresponding to the plurality of capacitors. Each of the plurality of third analog switches is connected between the other electrode of a corresponding capacitor and a third node. The third node receives a second reference voltage that is lower than the first reference voltage. The voltage comparator compares a voltage at the respective one electrodes of the plurality of capacitors with a third reference voltage. The state controller controls ON/OFF of the plurality of first analog switches, the plurality of second analog switches and the plurality of third analog switches based on the comparison result of the voltage comparator. Each of the plurality of second analog switches has an on-state resistance weighted with a prescribed weighting factor.
In the above successive comparison A-D converter, a second analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor, whereby a time constant of this capacitor can be reduced. As a result, the difference in time constant between the capacitors is reduced. This enables reduction in time required for charge redistribution, improving the A-D conversion speed.
Preferably, each of the plurality of second analog switches has an on-state resistance weighted with an inverse number of the weighting factor for the capacitance of a corresponding capacitor.
In the above successive comparison A-D converter, the respective time constants of the capacitors are equal to each other. Accordingly, the time required to charge/discharge each capacitor is the same. This prevents reduction in operation speed caused by the difference in time constant between the capacitors. Moreover, the A-D conversion can be improved while suppressing increase in circuit area.
Preferably, each of the plurality of second analog switches includes a MOS transistor. Each MOS transistor is connected between the other electrode of a corresponding capacitor and the second node. The MOS transistor included in one of the plurality of second analog switches and the MOS transistor included in another second analog switch have different channel widths and/or different channel lengths.
When the MOS transistor is operating in a linear region, the on-state resistance is inversely proportional to the channel width and is proportional to the channel length. In the above successive comparison A-D converter, the MOS transistor included in one second analog switch and the MOS transistor included in another second analog switch have different channel widths and/or different channel lengths. This enables the on-state resistance of these second analog switches to be weighted with different weighting factors. Accordingly, a second analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor. Moreover, the respective time constants of the capacitors can be made equal to each other.
Preferably, each of the plurality of second analog switches includes one or a plurality of fifth analog switches. One or the plurality of fifth analog switches are connected in parallel between the other electrode of a corresponding capacitor and the second node. The number of fifth analog switches included in one of the plurality of second analog switches is different from that included in another second analog switch.
The above successive comparison A-D converter enables the on-state resistance of one second analog switch and another second analog switch to be weighted with different weighting factors. Accordingly, a second analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor. Moreover, the respective time constants of the capacitors can be made equal to each other.
Preferably, each of the plurality of second analog switches includes a MOS transistor. Each MOS transistor is connected between the other electrode of a corresponding capacitor and the second node. A gate voltage to be applied to the MOS transistor included in one of the plurality of second analog switches when the MOS transistor is in an ON state is different from that to be applied to the MOS transistor included in another second analog switch when the MOS transistor is in an ON state.
When the MOS transistor is operating in a linear region, the on-state resistance is inversely proportional to the gate voltage. In the above successive comparison A-D converter, a gate voltage to be applied to the MOS transistor included in one second analog switch when the MOS transistor is in an ON state is different from that to be applied to the MOS transistor included in another second analog switch when the MOS transistor is in an ON state. This enables the on-state resistance of the second analog switches to be weighted with different weighting factors. Accordingly, a second analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor. Moreover, the respective time constants of the capacitors can be made equal to each other.
According to still another aspect of the present invention, a successive comparison A-D converter includes a plurality of capacitors, a plurality of first analog switches, a plurality of second analog switches, a plurality of third analog switches, a voltage comparator, and a state controller. The plurality of capacitors have their respective one electrodes connected to each other. Each of the plurality of capacitors has a capacitance weighted with a prescribed weighting factor. The plurality of first analog switches are provided corresponding to the plurality of capacitors. Each of the plurality of first analog switches is connected between the other electrode of a corresponding capacitor and a first node. The first node receives an analog input. The plurality of second analog switches are provided corresponding to the plurality of capacitors. Each of the plurality of second analog switches is connected between the other electrode of a corresponding capacitor and a second node. The second node receives a first reference voltage. The plurality of third analog switches are provided corresponding to the plurality of capacitors. Each of the plurality of third analog switches is connected between the other electrode of a corresponding capacitor and a third node. The third node receives a second reference voltage that is lower than the first reference voltage. The voltage comparator compares a voltage at the respective one electrodes of the plurality of capacitors with a third reference voltage. The state controller controls ON/OFF of the plurality of first analog switches, the plurality of second analog switches and the plurality of third analog switches based on the comparison result of the voltage comparator. Each of the plurality of third analog switches has an on-state resistance weighted with a prescribed weighting factor.
In the above successive comparison A-D converter, a third analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor, whereby a time constant of this capacitor can be reduced. As a result, the difference in time constant between the capacitors is reduced. This enables reduction in time required for charge redistribution, improving the A-D conversion speed.
Preferably, each of the plurality of third analog switches has an on-state resistance weighted with an inverse number of the weighting factor for the capacitance of a corresponding capacitor.
In the above successive comparison A-D converter, the respective time constants of the capacitors are equal to each other. Accordingly, the time required to charge/discharge each capacitor is the same. This prevents reduction in operation speed caused by the difference in time constant between the capacitors. Moreover, the A-D conversion can be improved while suppressing increase in circuit area.
Preferably, each of the plurality of third analog switches includes a MOS transistor. Each MOS transistor is connected between the other electrode of a corresponding capacitor and the third node. The MOS transistor included in one of the plurality of third analog switches and the MOS transistor included in another third analog switch have different channel widths and/or different channel lengths.
When the MOS transistor is operating in a linear region, the on-state resistance is inversely proportional to the channel width and is proportional to the channel length. In the above successive comparison A-D converter, the MOS transistor included in one third analog switch and the MOS transistor included in another third analog switch have different channel widths and/or different channel lengths. This enables the on-state resistance of these third analog switches to be weighted with different weighting factors. Accordingly, a third analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor. Moreover, the respective time constants of the capacitors can be made equal to each other.
Preferably, each of the plurality of third analog switches includes one or a plurality of sixth analog switches. One or the plurality of sixth analog switches are connected in parallel between the other electrode of a corresponding capacitor and the third node. The number of sixth analog switches included in one of the plurality of third analog switches is different from that included in another third analog switch.
The above successive comparison A-D converter enables the on-state resistance of one third analog switch and another third analog switch to be weighted with different weighting factors. Accordingly, a third analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor. Moreover, the respective time constants of the capacitors can be made equal to each other.
Preferably, each of the plurality of third analog switches includes a MOS transistor. Each MOS transistor is connected between the other electrode of a corresponding capacitor and the third node. A gate voltage to be applied to the MOS transistor included in one of the plurality of third analog switches when the MOS transistor is in an ON state is different from that to be applied to the MOS transistor included in another third analog switch when the MOS transistor is in an ON state.
When the MOS transistor is operating in a linear region, the on-state resistance is inversely proportional to the gate voltage. In the above successive comparison A-D converter, a gate voltage to be applied to the MOS transistor included in one third analog switch when the MOS transistor is in an ON state is different from that to be applied to the MOS transistor included in another third analog switch when the MOS transistor is in an ON state. This enables the on-state resistance of these third analog switches to be weighted with different weighting factors. Accordingly, a third analog switch corresponding to a capacitor having a capacitance weighted with a larger weighting factor can be made to have an on-state resistance weighted with a smaller weighting factor. Moreover, the respective time constants of the capacitors can be made equal to each other.